Buffer circuits (e.g., output buffers, input buffers, and bidirectional buffers) are employed in a variety of electronic devices and applications. Each of these buffer circuits typically includes an output driver stage including a p-type metal-oxide-semiconductor (PMOS) device, MPO, and an n-type metal-oxide-semiconductor (NMOS) device, MNO, connected to an external input/output (IO) pad at node N1, as shown in FIG. 1. Devices MPO and MNO are driven by control signals PG and NG, respectively, generated by control circuitry in the buffer circuit. Generally, MPO and MNO are large transistors which are capable of providing the currents that are associated with driving off-chip loads.
In some applications, a buffer circuit running at a particular supply voltage, such as VDDIO (e.g., 3.3 volts), may be subjected to a voltage potential, PAD, at the IO pad (node N1) which is substantially higher than what is supported by the semiconductor process technology used to fabricate the buffer circuit. Essentially all PMOS and NMOS devices have associated therewith parasitic diodes, DP and DN, respectively, between their source/drains and the underlying well or substrate. When the voltage PAD exceeds the supply voltage VDDIO by about a threshold voltage of the PMOS device MPO, the parasitic diode DP associated with MPO will undesirably become forward-biased, thereby conducting a large current. This large diode current can trigger latch-up or, at a minimum, cause significant parasitic currents to flow.
To avoid forward biasing the parasitic diode DP associated with the output stage of the buffer circuit when PAD is substantially greater than VDDIO, it is known to place the PMOS device MPO in a floating n-well (see, e.g., U.S. Pat. No. 5,160,855, the disclosure of which is incorporated by reference herein). The well of a given device is typically defined by a voltage potential at a bulk of the device. Typically, a special voltage generator circuit 200 is used, an example of which is depicted in FIG. 2, which generates a voltage, VFLT, at an output node N2 of the circuit that is equal to the higher of either VDDIO or PAD. Node N2 of the voltage generator circuit 200 is connected to the bulk of PMOS device MPO (FIG. 1), so that the well of the MPO is always biased to the potential VFLT. However, when PAD is within a threshold voltage above or below VDDIO, the two PMOS devices, MPF1 and MPF2, generating the n-well bias voltage VFLT will be turned off, and thus the n-well in which PMOS device MPO is formed will truly be floating. Circuits having floating wells are generally highly susceptible to latch-up, particularly during latch-up testing and even during normal operation of the circuit.
Accordingly, there exists a need for an improved floating well circuit that does not suffer from one or more of the problems exhibited by conventional floating well circuits.